#ifndef __CLK_SUN9IW1_H
#define __CLK_SUN9IW1_H
 
 
#define LOSC_CLK "losc"
#define HOSC_CLK "hosc"
#define HOSC_750_CLK "hosc_750"
#define PLL1_CLK "pll1"
#define PLL2_CLK "pll2"
#define PLL3_CLK "pll3"
#define PLL4_CLK "pll4"
#define PLL5_CLK "pll5"
#define PLL6_CLK "pll6"
#define PLL7_CLK "pll7"
#define PLL8_CLK "pll8"
#define PLL9_CLK "pll9"
#define PLL10_CLK "pll10"
#define PLL11_CLK "pll11"
#define PLL12_CLK "pll12"
#define CLUSTER0_CLK "cluster0"
#define CLUSTER1_CLK "cluster1"
#define AXI0_CLK "axi0"
#define AXI1_CLK "axi1"
#define GT_CLK "gt"
#define AHB0_CLK "ahb0"
#define AHB1_CLK "ahb1"
#define AHB2_CLK "ahb2"
#define APB0_CLK "apb0"
#define APB1_CLK "apb1"
#define CCI400_CLK "cci400"
#define ATS_CLK "ats"
#define TRACE_CLK "trace"
#define OUTA_CLK "outa"
#define OUTB_CLK "outb"
#define NAND0_0_CLK "nand0_0"
#define NAND0_1_CLK "nand0_1"
#define NAND1_0_CLK "nand1_0"
#define NAND1_1_CLK "nand1_1"
#define SDMMC0_CLK "sdmmc0"
#define SDMMC1_CLK "sdmmc1"
#define SDMMC2_CLK "sdmmc2"
#define SDMMC3_CLK "sdmmc3"
#define TS_CLK "ts"
#define SS_CLK "ss"
#define SPI0_CLK "spi0"
#define SPI1_CLK "spi1"
#define SPI2_CLK "spi2"
#define SPI3_CLK "spi3"
#define I2S0_CLK "i2s0"
#define I2S1_CLK "i2s1"
#define SPDIF_CLK "spdif"
#define USBOTG_CLK "usbotg"
#define USBOTGPHY_CLK "usbotgphy"
#define USBHCI_CLK "usbhci"
#define SDR0_CLK "sdr0"
#define DE_CLK "de"
#define EDP_CLK "edp"
#define MP_CLK "mp"
#define LCD0_CLK "lcd0"
#define LCD1_CLK "lcd1"
#define MIPI_DSI0_CLK "mipi_dsi0"
#define MIPI_DSI1_CLK "mipi_dsi1"
#define HDMI_CLK "hdmi"
#define HDMI_SLOW_CLK "hdmi_slow"
#define MIPI_CSI_CLK "mipi_csi"
#define CSI_ISP_CLK "csi_isp"
#define CSI_MISC_CLK "csi_misc"
#define CSI0_MCLK_CLK "csi0_mclk"
#define CSI1_MCLK_CLK "csi1_mclk"
#define FD_CLK "fd"
#define VE_CLK "ve"
#define AVS_CLK "avs"
#define GPUCORE_CLK "gpucore"
#define GPUMEM_CLK "gpumem"
#define GPUAXI_CLK "gpuaxi"
#define SATA_CLK "sata"
#define AC97_CLK "ac97"
#define MIPI_HSI_CLK "mipi_hsi"
#define GPADC_CLK "gpadc"
#define CIRTX_CLK "cirtx"
#define SDRAM_CLK "sdram"
#define DMA_CLK "dma"
#define HSTMR_CLK "hstmr"
#define SPINLOCK_CLK "spinlock"
#define MSGBOX_CLK "msgbox"
#define GMAC_CLK "gmac"
#define LVDS_CLK "lvds"
#define TWD_CLK "twd"
#define LRADC_CLK "lradc"
#define PIO_CLK "pio"
#define TWI0_CLK "twi0"
#define TWI1_CLK "twi1"
#define TWI2_CLK "twi2"
#define TWI3_CLK "twi3"
#define TWI4_CLK "twi4"
#define UART0_CLK "uart0"
#define UART1_CLK "uart1"
#define UART2_CLK "uart2"
#define UART3_CLK "uart3"
#define UART4_CLK "uart4"
#define UART5_CLK "uart5"
#define CPUR1W_CLK "cpur1w"
#define CPURCIR_CLK "cpurcir"
#define CPURI2S0_CLK "cpuri2s0"
#define CPURI2S1_CLK "cpuri2s1"
#define CPURVDDVE_CLK "cpurvddve"
 
 
#endif
